000			00483nam a2200181Ia 4500
008			240220s9999 xx 000 0 und d
041			_aENG
082			_a621.392
100			_aSutherland Stuart
245		0	_aRTL modeling with system verilog for simulation and synthesis
245		0	_bUsing system verilog for ASIC and FPGA design
260			_aOregon
260			_b"Sutherland HDL, Inc"
260			_c2021
365			_b10319.5
650			_aETC_ELECTRONICS
942			_cEB
999			_c12983 _d12983