RTL modeling with system verilog for simulation and synthesis (Record no. 12983)

MARC details
000 -LEADER
fixed length control field 00483nam a2200181Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 240220s9999 xx 000 0 und d
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title ENG
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.392
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Sutherland Stuart
245 #0 - TITLE STATEMENT
Title RTL modeling with system verilog for simulation and synthesis
245 #0 - TITLE STATEMENT
Remainder of title Using system verilog for ASIC and FPGA design
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Oregon
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Name of publisher, distributor, etc. "Sutherland HDL, Inc"
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2021
365 ## - TRADE PRICE
Price amount 10319.5
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element ETC_ELECTRONICS
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type EBOOKS
Holdings
Date last seen Total checkouts Full call number Accession Number Cost, replacement price Price effective from Koha item type Section Lost status Damaged status Not for loan Collection Withdrawn status Home library Current library Shelving location Date acquired Cost, normal purchase price Bill No Bill Date Cat No Currency
2024-02-20   621.392 E02517 10319.50 2024-02-20 EBOOKS EBOOKS       Text Book   Rajarambapu Institute of Technology, Rajaramnagar Rajarambapu Institute of Technology, Rajaramnagar DIGITAL LIBRARY 2021-03-29 10319.50 2140481 08 February 2021 44307 INR

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